Developing a signal-integrity & power-Integrity co-simulation platform

• 主要作者: Tanudjaja, Delbert Sandy
• 其他作者: See Kye Yak
• 格式: Final Year Project
• 語言: English
• 出版: 2016
• 主題: DRNTU::Engineering
• 在線閱讀: http://hdl.handle.net/10356/67919
• 機構: Nanyang Technological University

This issue of ringing, or in other words, crosstalk still persists in today‟s technologically advanced world. With sufficient simulation and testing, there should not be any excuse for problems caused by ringing. The signal integrity (SI) simulation process is a complexed one. However, with the necessary tools provided and a good simulation software, it can be accomplished with relative ease. The I/O Buffer Information Specification (IBIS) is an international standard for the electrical specification of chip drivers and receivers. It provides a standard file format for recording vital parameters which are optimally suited for automatic calculation of ringing and crosstalk. It does come with some drawbacks though, and one would be a distinct lack of support for IBIS models among many chip vendors. Nonetheless, this flaw does not mask its ability to produce accurate, clear simulations of high-speed ringing and crosstalk patterns. (Johnson, 2003) When many ICs switch simultaneously, the transient currents drawn from the power supply will generate noise on the power distribution network (PDN). Such noise, if not properly suppressed, will compromise the operation of the digital circuit. Hence, the main objective of this project will be to study and investigate the impact of such noise and implement a platform in which PCB designers can tweak parameters for more comprehensive simulations in future.