Low ripple on-chip switched capacitor DC-DC converter remove

• Main Author: Li, Ling Lu
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/67966
• Institution: Nanyang Technological University

Due to the fast developing technologies of portable electronic devices, more and more sophisticated devices demanding a refined and accurate supply voltage. With that in mind, here in this final year project, a newly proposed switched capacitor DC-DC Converter with suppressed output voltage ripple is presented. The proposed SC converter achieves reduced output voltage ripple through continuous control of the charging/discharging current during both switching phases. The integrated system includes a switched-capacitor voltage divider power stage, a clock generator implemented as a current-starved ring oscillator and a nested-current mirror error amplifier. The nested-current mirror amplifier compares the output voltage with the reference voltage, and the output is used to control one of the power switches in each phase to regulate continuous current delivered to the output. With this continuous control scheme, switched capacitor DC-DC converter is able to deliver a stable desired output voltage. The proposed switched capacitor DC-DC converter is implemented in Cadence simulation environment and particular AMS C18A6 technology. The converter operates at frequency range from 0.7 MHz to 7.5MHz. The flying capacitor of DC-DC converter is 150pf, the converter is able to deliver a maximum of 10mA load current. The simulation result shows output voltage ripple has been reduced to around 3mV. Compared to the conventional design, voltage ripple has decreased significantly.