A fast low dropout regulator for digital systems

Low Dropout (LDO) voltage regulator is an important building block, especially power management ICs for SOC applications, due to popular portable devices. An LDO can provide a regulated, stable voltage for subsequent circuits with various loading conditions. For a digital system, fast response with...

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Main Author: Jiang, Yushan
Other Authors: Chan Pak Kwong
Format: Final Year Project
Language:English
Published: 2016
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Online Access:http://hdl.handle.net/10356/68332
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-683322023-07-07T16:03:53Z A fast low dropout regulator for digital systems Jiang, Yushan Chan Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering Low Dropout (LDO) voltage regulator is an important building block, especially power management ICs for SOC applications, due to popular portable devices. An LDO can provide a regulated, stable voltage for subsequent circuits with various loading conditions. For a digital system, fast response with small settling time and low noise are essential to avoid system error. Precise output voltage and good power efficiency are major consideration for low power devices. The proposed LDO regulator provides a 200mV dropout voltage with 0.9V supply voltage. A Flipped Voltage Follower (FVF) based voltage regulator with output capacitor-less characteristic is used. This meets the need of reducing chip area. With an ac coupling network to detect the spike and to response in a fast loop, fast transient performance is achieved. The compensation technique is based on the combination of Miller compensation and DFC compensation. It ensures the stability of the LDO’s function. Besides, additional gain stage in feedback loop is employed to achieve high loop gain, leading to good load and line regulations. Validated by UMC 65nm CMOS process, the proposed LDO regulator achieves the load capacitance driving capability up to 3nF. It can achieve the stability with a driving load current ranging from 0mA to 10mA, whilst consuming a low quiescent current less than 20µA. Furthermore, the load transient response with <1µs setting time is achieved with minimized voltage spike. This is useful for driving on-chip low-power microcontroller system. Comparing the simulation results with that of other reported capacitor-less LDO regulators, the proposed LDO regulator has a better figure of merit (FOM) and has offered other comparable performance metrics. Bachelor of Engineering 2016-05-25T06:47:02Z 2016-05-25T06:47:02Z 2016 Final Year Project (FYP) http://hdl.handle.net/10356/68332 en Nanyang Technological University 55 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Jiang, Yushan
A fast low dropout regulator for digital systems
description Low Dropout (LDO) voltage regulator is an important building block, especially power management ICs for SOC applications, due to popular portable devices. An LDO can provide a regulated, stable voltage for subsequent circuits with various loading conditions. For a digital system, fast response with small settling time and low noise are essential to avoid system error. Precise output voltage and good power efficiency are major consideration for low power devices. The proposed LDO regulator provides a 200mV dropout voltage with 0.9V supply voltage. A Flipped Voltage Follower (FVF) based voltage regulator with output capacitor-less characteristic is used. This meets the need of reducing chip area. With an ac coupling network to detect the spike and to response in a fast loop, fast transient performance is achieved. The compensation technique is based on the combination of Miller compensation and DFC compensation. It ensures the stability of the LDO’s function. Besides, additional gain stage in feedback loop is employed to achieve high loop gain, leading to good load and line regulations. Validated by UMC 65nm CMOS process, the proposed LDO regulator achieves the load capacitance driving capability up to 3nF. It can achieve the stability with a driving load current ranging from 0mA to 10mA, whilst consuming a low quiescent current less than 20µA. Furthermore, the load transient response with <1µs setting time is achieved with minimized voltage spike. This is useful for driving on-chip low-power microcontroller system. Comparing the simulation results with that of other reported capacitor-less LDO regulators, the proposed LDO regulator has a better figure of merit (FOM) and has offered other comparable performance metrics.
author2 Chan Pak Kwong
author_facet Chan Pak Kwong
Jiang, Yushan
format Final Year Project
author Jiang, Yushan
author_sort Jiang, Yushan
title A fast low dropout regulator for digital systems
title_short A fast low dropout regulator for digital systems
title_full A fast low dropout regulator for digital systems
title_fullStr A fast low dropout regulator for digital systems
title_full_unstemmed A fast low dropout regulator for digital systems
title_sort fast low dropout regulator for digital systems
publishDate 2016
url http://hdl.handle.net/10356/68332
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