Dual mode CMOS logic circuits

For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic...

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Main Author: Liu, Kai
Other Authors: Lau Kim Teen
Format: Theses and Dissertations
Language:English
Published: 2016
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Online Access:http://hdl.handle.net/10356/68706
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-687062023-07-04T15:05:03Z Dual mode CMOS logic circuits Liu, Kai Lau Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic counterparts, due to the fact that the delay o f low voltage CMOS has been degraded significantly, it is unpractical in many applications. So a novel logic family called dual mode logic (DML) which can be switched between static and dynamic operation modes with a clock control signal is introduced. In the dissertation I introduce the basic DML circuit structure as well as the operation. DML gates present the advantages o f both static and dynamic gates, so DML gates allow these gates to achieve ultra-low power while operating in the static mode, and also high performance in the dynamic mode. The task is to analyze the typical DML gates and study their properties in comparison with conventional ones. And possible application in full adder design is studied; the simulation shall be conducted under different supply voltage and signal frequency, and simulation results will be analyzed and compared. Master of Science (Electronics) 2016-05-31T02:21:01Z 2016-05-31T02:21:01Z 2016 Thesis http://hdl.handle.net/10356/68706 en 121 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Liu, Kai
Dual mode CMOS logic circuits
description For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic counterparts, due to the fact that the delay o f low voltage CMOS has been degraded significantly, it is unpractical in many applications. So a novel logic family called dual mode logic (DML) which can be switched between static and dynamic operation modes with a clock control signal is introduced. In the dissertation I introduce the basic DML circuit structure as well as the operation. DML gates present the advantages o f both static and dynamic gates, so DML gates allow these gates to achieve ultra-low power while operating in the static mode, and also high performance in the dynamic mode. The task is to analyze the typical DML gates and study their properties in comparison with conventional ones. And possible application in full adder design is studied; the simulation shall be conducted under different supply voltage and signal frequency, and simulation results will be analyzed and compared.
author2 Lau Kim Teen
author_facet Lau Kim Teen
Liu, Kai
format Theses and Dissertations
author Liu, Kai
author_sort Liu, Kai
title Dual mode CMOS logic circuits
title_short Dual mode CMOS logic circuits
title_full Dual mode CMOS logic circuits
title_fullStr Dual mode CMOS logic circuits
title_full_unstemmed Dual mode CMOS logic circuits
title_sort dual mode cmos logic circuits
publishDate 2016
url http://hdl.handle.net/10356/68706
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