Design of continuous-time delta sigma converters for high fidelity audio applications

Audio signal processing is one system that demands high resolution A/D converters. The healthy human ear can decipher sound with intensities varying from 0~3dB to more than 160dB (Sound Pressure Level) SPL with a theoretical frequency bandwidth of up to 20~25kHz. Traditional audio signal processing...

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Main Author: Leow, Yoon Hwee
Other Authors: Siek Liter
Format: Theses and Dissertations
Language:English
Published: 2016
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Online Access:https://hdl.handle.net/10356/69095
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-69095
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institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Leow, Yoon Hwee
Design of continuous-time delta sigma converters for high fidelity audio applications
description Audio signal processing is one system that demands high resolution A/D converters. The healthy human ear can decipher sound with intensities varying from 0~3dB to more than 160dB (Sound Pressure Level) SPL with a theoretical frequency bandwidth of up to 20~25kHz. Traditional audio signal processing channels rely on standalone modules where each component is optimized in their own chosen technology. Consequentially, high fidelity but huge products result. The luxury of having a higher supply voltage for the noise sensitive analog circuitries whereas a lower supply voltage in speed demanding digital processing circuits addressed the ADC resolution. Recent audio codec systems present a set of different requirements. Heavy Digital Signal Processing (DSP) fueled with cost and aesthetics of the final product demand a consolidation of components along the audio signal processing channel. The Continuous-Time (CT) Δ∑ modulator offers a number of advantages over its discrete counterpart in some fields of application. Traditionally, the DT Δ∑ modulator has dominated this market. The moderately low bandwidth requirement (i.e. 20 kHz–25 kHz) means the design of OTAs with a reasonable speed consuming an acceptable power can still be achieved. In order to maximize the suppression of quantization noise, ADC designers resort usually to either high order (4-6) or multibit feedback DAC structures; not to mention the usage of high OSR of above 64. However in the advent of nanoscale technology, the former apparent choice of DT architectures becomes less justifiable. Feature size down scaling with technology advancements gives rise to weaker devices that can only tolerate low supply voltages. The input dynamic range of the frontend Sample and Hold (S/H) ADC buffer has to be maximized under the constrained VDD supply while maintaining linearity. This warrants the use of more complicated switching control techniques such as boot strapping. On the other hand, the inputs to a CT Δ∑ modulator can be built without a S/H buffer with the possibility of reaching high input dynamic ranges via linear resistors of a opamp RC integrator. This generates interest in the research for high resolution ADCs for high fidelity audio applications in advanced nanoscale technologies. This work researches into the design of CT Δ∑ modulators targeted for high fidelity audio applications. The literature review chapter presents an evolution of oversampling CT Δ∑ modulators in this field of area. Subsequently, high level detailed modelling will be discussed leading to the development of a circuit-based model for rapid verification that shorten optimization turn-around time. Two CT Δ∑ modulators with different architectural approaches are presented. Chapter 5 described the realization of a 4th order CT Δ∑ modulator. System level non-idealities such as clock jitter uncertainties and process variation tolerance were discussed and relaxed with proposed circuitries. This modulator, implemented in 180nm technology with a supply of 1.5V was fully verified in simulation and achieved an SNR/SNDR of 90.6dB/88.7dB with a reasonable input dynamic range of differential peak-to-peak of 2V while consuming a current consumption of only 153µA. Chapter 6 proposed a third order audio CT Δ∑ modulator developed in advance 65nm standard CMOS technology. To enhance the NTF, Noise Coupling (NC) was applied in a second order CIFF architecture. The input dynamic range achieved a differential peak-to-peak voltage of 2V even at the ultra-low supply of 1V considering such a high resolution design target. The modulator achieved a measured DR/SNR/SNDR of 103.1dB/100.1dB/95.2dB while dissipating 0.8mW.
author2 Siek Liter
author_facet Siek Liter
Leow, Yoon Hwee
format Theses and Dissertations
author Leow, Yoon Hwee
author_sort Leow, Yoon Hwee
title Design of continuous-time delta sigma converters for high fidelity audio applications
title_short Design of continuous-time delta sigma converters for high fidelity audio applications
title_full Design of continuous-time delta sigma converters for high fidelity audio applications
title_fullStr Design of continuous-time delta sigma converters for high fidelity audio applications
title_full_unstemmed Design of continuous-time delta sigma converters for high fidelity audio applications
title_sort design of continuous-time delta sigma converters for high fidelity audio applications
publishDate 2016
url https://hdl.handle.net/10356/69095
_version_ 1772826308236017664
spelling sg-ntu-dr.10356-690952023-07-04T16:12:52Z Design of continuous-time delta sigma converters for high fidelity audio applications Leow, Yoon Hwee Siek Liter School of Electrical and Electronic Engineering DRNTU::Engineering Audio signal processing is one system that demands high resolution A/D converters. The healthy human ear can decipher sound with intensities varying from 0~3dB to more than 160dB (Sound Pressure Level) SPL with a theoretical frequency bandwidth of up to 20~25kHz. Traditional audio signal processing channels rely on standalone modules where each component is optimized in their own chosen technology. Consequentially, high fidelity but huge products result. The luxury of having a higher supply voltage for the noise sensitive analog circuitries whereas a lower supply voltage in speed demanding digital processing circuits addressed the ADC resolution. Recent audio codec systems present a set of different requirements. Heavy Digital Signal Processing (DSP) fueled with cost and aesthetics of the final product demand a consolidation of components along the audio signal processing channel. The Continuous-Time (CT) Δ∑ modulator offers a number of advantages over its discrete counterpart in some fields of application. Traditionally, the DT Δ∑ modulator has dominated this market. The moderately low bandwidth requirement (i.e. 20 kHz–25 kHz) means the design of OTAs with a reasonable speed consuming an acceptable power can still be achieved. In order to maximize the suppression of quantization noise, ADC designers resort usually to either high order (4-6) or multibit feedback DAC structures; not to mention the usage of high OSR of above 64. However in the advent of nanoscale technology, the former apparent choice of DT architectures becomes less justifiable. Feature size down scaling with technology advancements gives rise to weaker devices that can only tolerate low supply voltages. The input dynamic range of the frontend Sample and Hold (S/H) ADC buffer has to be maximized under the constrained VDD supply while maintaining linearity. This warrants the use of more complicated switching control techniques such as boot strapping. On the other hand, the inputs to a CT Δ∑ modulator can be built without a S/H buffer with the possibility of reaching high input dynamic ranges via linear resistors of a opamp RC integrator. This generates interest in the research for high resolution ADCs for high fidelity audio applications in advanced nanoscale technologies. This work researches into the design of CT Δ∑ modulators targeted for high fidelity audio applications. The literature review chapter presents an evolution of oversampling CT Δ∑ modulators in this field of area. Subsequently, high level detailed modelling will be discussed leading to the development of a circuit-based model for rapid verification that shorten optimization turn-around time. Two CT Δ∑ modulators with different architectural approaches are presented. Chapter 5 described the realization of a 4th order CT Δ∑ modulator. System level non-idealities such as clock jitter uncertainties and process variation tolerance were discussed and relaxed with proposed circuitries. This modulator, implemented in 180nm technology with a supply of 1.5V was fully verified in simulation and achieved an SNR/SNDR of 90.6dB/88.7dB with a reasonable input dynamic range of differential peak-to-peak of 2V while consuming a current consumption of only 153µA. Chapter 6 proposed a third order audio CT Δ∑ modulator developed in advance 65nm standard CMOS technology. To enhance the NTF, Noise Coupling (NC) was applied in a second order CIFF architecture. The input dynamic range achieved a differential peak-to-peak voltage of 2V even at the ultra-low supply of 1V considering such a high resolution design target. The modulator achieved a measured DR/SNR/SNDR of 103.1dB/100.1dB/95.2dB while dissipating 0.8mW. DOCTOR OF PHILOSOPHY (EEE) 2016-10-27T07:41:04Z 2016-10-27T07:41:04Z 2016 Thesis Leow, Y. H. (2016). Design of continuous-time delta sigma converters for high fidelity audio applications. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/69095 10.32657/10356/69095 en 221 p. application/pdf