Educational simulator for Cache and Virtual addressing

• Main Author: Paramita, Aryani
• Other Authors: Smitha Kavallur Pisharath Gopi
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/69143
• Institution: Nanyang Technological University

With the increasing computational demand, efficiency and effectiveness of cache and virtual memory become an important area to be looked into. By utilising the correct caching method, an architecture would achieve maximum performance with minimum resources. To choose the appropriate configuration, the fundamental of cache and virtual memory must be understood by every engineer. This project aims to deliver a simulator to visualize cache and virtual memory processes better. The simulator is built for Direct Mapped Cache, Fully Associative Cache, and Set Associative Caches. Replacement policy such as Least Recently Used and First in First out is also being implemented in the simulator. Analysis and comparison of various cache is also made available and supported by interactive graph. Lastly, the simulator has Virtual Memory Simulator dedicated to visualise virtual memory section. The objective of this report is to document the development process of the simulator that consists of two environments: Java-based environment and Web based environment. It will also serve as guides and further explanation on the simulator, making it clearer and more fruitful for the users learning about cache and virtual memory.