FPGA-efficient feature detector for real-time vision-based applications

• Main Author: Chandrasekar, Srivatsan
• Other Authors: Lam Siew Kei
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: http://hdl.handle.net/10356/70417
• Institution: Nanyang Technological University

Feature detection, extraction and matching are integral to most computer vision applications, and hence have become topics of broad and current interest. Corners or interest points are pervasive and important features. Extraction of these features minimizes processing data and is commonly used in several vision-based applications. There are several interest point detectors available in literature, out of which the Harris corner detector is one of the most commonly used ones. This project aims to implement a low-complexity pruning technique for the Harris corner detector in hardware. The detector involves the computation of a corner measure for every pixel of the image, which involves several computationally intensive operations. The pruning technique selects a small subset of candidate pixels by approximating the corner measure. The complex corner measure is then calculated only for this subset of pixels. The results of the implementation of the pruning method for the Harris corner detector show that the corner measure is calculated only for a small percentage of the total number of pixels in the image.