Study and analysis of neuromorphic processors and applications

• Main Author: Huang, Jingyao
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/71666
• Institution: Nanyang Technological University

Neuromorphic computing is emerging as a very promising computing technology, which is very efficient in the artificial intelligent (AI) applications of machine vision, hearing, pattern recognition and learning. Neuromorphic processor, as a new generation of computing platform, has emerged with many advantages against conventional von Neumann architectures processor. Due to its special architecture where the memory and processing elements are not separated, neuromorphic processors can implement convolution neural network (CNN) structure with higher performance, lower energy consumption, or smaller form factor. In this project, review of artificial neural network theory inspirited by biological neural network is carried out. Because of the wide applications including image recognition and natural language processing are required to be implemented efficient hardware architecture, this project focus on study and development of CNN algorithm and architecture design. Two neural network structures, i.e., a single hidden layer neural network and a multilayer CNN are studied and implemented in MATLAB to implement hand written digits recognition. The comparison of these two algorithms is done by performance and computation evaluation. Compared with the single hidden layer neural network used, the multilayer CNN used 75% less weights and gets a higher accuracy (>2%), which is much more efficient for hardware design. The-state-of-the-art neuromorphic processors implementing CNN algorithms for image and video recognition applications are reviewed and studied. Finally, we design a CNN neuromorphic processor architecture for handwritten digits recognition. Hardware resources, computation complexity, and performance of the architecture design is analyzed and discussed. The processing time required for performing a digit recognition task is 13610 cycles. The processing throughput is up to 201 pixels/cycle.