A 40nm CMOS high PSRR differential difference amplifier for sensor applications
PSRR is becoming increasingly crucial as higher integration demands for noisy digital circuitry to packed closely to sensitive analog blocks. A high PSRR and low power amplifier is needed to drive a resistive 100 kΩ and capacitive 50 pF load over low frequencies as analog surrounding do not react at...
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2017
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| Online Access: | http://hdl.handle.net/10356/71728 |
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sg-ntu-dr.10356-717282023-07-07T17:35:00Z A 40nm CMOS high PSRR differential difference amplifier for sensor applications Chong, Chean Hwa Chan Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering PSRR is becoming increasingly crucial as higher integration demands for noisy digital circuitry to packed closely to sensitive analog blocks. A high PSRR and low power amplifier is needed to drive a resistive 100 kΩ and capacitive 50 pF load over low frequencies as analog surrounding do not react at a high rate. This project has presented a three-stage differential difference amplifier (DDA) with PSRR of -92 dB near DC and -64 dB at 1 kHz. The DDA utilised supply independent biasing circuit for stable current output, a level shift flipped voltage follower (LSFVF) structured low-dropout (LDO) regulator to stabilise the supply voltage and a low pass filter (LPF) to attenuate all AC power supply ripple. Bachelor of Engineering 2017-05-19T01:58:23Z 2017-05-19T01:58:23Z 2017 Final Year Project (FYP) http://hdl.handle.net/10356/71728 en Nanyang Technological University 55 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Chong, Chean Hwa A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| description |
PSRR is becoming increasingly crucial as higher integration demands for noisy digital circuitry to packed closely to sensitive analog blocks. A high PSRR and low power amplifier is needed to drive a resistive 100 kΩ and capacitive 50 pF load over low frequencies as analog surrounding do not react at a high rate. This project has presented a three-stage differential difference amplifier (DDA) with PSRR of -92 dB near DC and -64 dB at 1 kHz. The DDA utilised supply independent biasing circuit for stable current output, a level shift flipped voltage follower (LSFVF) structured low-dropout (LDO) regulator to stabilise the supply voltage and a low pass filter (LPF) to attenuate all AC power supply ripple. |
| author2 |
Chan Pak Kwong |
| author_facet |
Chan Pak Kwong Chong, Chean Hwa |
| format |
Final Year Project |
| author |
Chong, Chean Hwa |
| author_sort |
Chong, Chean Hwa |
| title |
A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| title_short |
A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| title_full |
A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| title_fullStr |
A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| title_full_unstemmed |
A 40nm CMOS high PSRR differential difference amplifier for sensor applications |
| title_sort |
40nm cmos high psrr differential difference amplifier for sensor applications |
| publishDate |
2017 |
| url |
http://hdl.handle.net/10356/71728 |
| _version_ |
1772825256242708480 |