Power analysis of multi-protocol serdes

• Main Author: Francesco, Asola
• Other Authors: Lim Meng Hiot
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73115
• Institution: Nanyang Technological University

SerDes (serializer/deserializer) transceiver blocks are used in high-speed serial links. The serialization and de-serialization of data, together with the high rate at which they are performed in recent communication standards that produces transfer rates in the order of GT/s (Giga Transfers per second), make the SerDes block one of the most critical elements to consider for the overall power consumption of a system. Moreover, since SerDes power budget is directly related to the type of protocol used in the serial link, power performance becomes crucial for multi-protocol SerDes, where multiple interconnects can run different standards with diverse power consumption (e.g. PCIe, USB and SATA). The objective of this thesis is to provide a detailed power analysis of these multiprotocol SerDes, as well as to present a test case consisting of a SerDes for a PCIe high-speed serial link and give some insights on the possible improvements on power consumption. Finally, the results show how multi-protocol SerDes achieve power reduction and in particular how PCIe influences the multi-protocol SerDes behaviour in low power states.