Analysis and design of RSSI in the RF receiver chain

• Main Author: Bhaskar Yashaswini
• Other Authors: Siek Liter
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73123
• Institution: Nanyang Technological University

With the research and development in VLSI technology, the RF transceivers used in communication systems have greatly shrunk in size thus making their implementation in portable devices a reality. After its travel in the terrain, the signal must be detected by the antenna & RF receiver built in these small devices. When the signal travels through the free space, it undergoes attenuation & losses and faces interferences. The Received Signal Strength Indicator (RSSI) is used commonly in the RF receiver to measure power in the signal that is received by the antenna, after possible losses and interferences. RSSI, together with AGC, will set the gain of the receiver chain. Based on the measured signal power by the RSSI, AGC will tune the gain of LNA. Accordingly, LNA will enhance the power of incoming signals appropriately. This dissertation presents the CMOS design of such a RSSI block implemented in the RF receiver chain, which is used in low-power applications such as BLE or ZigBee. IFA and rectifiers form the basic building blocks of RSSI that are constructed with much care in this design. Cascaded structure of IFA is used and the output of each IFA is rectified. Few more accessories like chopper and comparators are added to these basic building blocks to meet the design specifications. Although, the front-end chopper is implemented for the IFA in order to perform chopper stabilization (CHS), there are no explicit circuits of de-chopper and low pass filter in the circuit that form the usual chopper stabilized amplifier structure. The novelty of this design is that, the de-chopper operation is internally performed by the rectifier that tracks the signal envelope. The comparator is designed to have bandwidth constraints and hence performs low-pass filtering. The circuit is operated at 1.1V supply voltage and has the maximum power consumption of 330 µW. The intermediate frequency of 8 MHz is chosen for the operation. This RSSI gives 72 dB of linear-log conversion and simulation results show that the circuit can detect signal having the power as low as -95 dBm. An option to even vary this input signal range that can be detected is facilitated. The design is implemented in 55 nm CMOS technology.