Analysis and design of high-speed digital-to-analog converters

• Main Author: Juanda
• Other Authors: Chang Joseph Sylvester
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73389
• Institution: Nanyang Technological University

This Ph.D. thesis pertains to the investigation, design, and monolithic realization of GHz Digital-to-Analog Converters (DACs). State-of-the-art DACs rely heavily on complex digital approaches (calibrations or dynamic-element-matching (DEM)) to achieve high linearity. However, these DACs undesirably suffer from inherent drawbacks such as high switching noise, long (time) latency, and complex GHz synchronization. Consequently, GS/s DACs with innate accuracy (i.e., without calibrations or DEM) are particularly attractive. However, the design of GS/s DACs with innate accuracy is challenging as it usually involves numerous fine-tuning due to sophisticated (often intractable) design trade-offs and the degraded transistor performance at GHz. Further, the testing and verification of GS/s DACs are challenging because of the difficulty associated with the generation of high-speed digital input patterns. To resolve some the aforesaid DAC design challenges, we investigate the relationships between several critical linearity parameters (e.g., Integral Nonlinearity (INL), Differential Nonlinearity (DNL), Spurious-Free Dynamic Range (SFDR), etc.) and the design parameters (e.g., output impedance, matching, etc.) of current-steering DAC (CS-DAC) by means of analytical analysis and comprehensive simulations. We derived an analytical relationship between the output impedance and INL, and modeled the relationship between the output impedance and SFDR. On this basis, we propose a design methodology to analytically estimate the requirements of several critical design parameters and thereafter the optimization thereto. This reduces the number of design iterations and the ensuing design effort. Further, we propose a novel design technique to decouple the aforesaid design trade-offs, leading to the opportunity for the design of higher-optimized DACs with innate accuracy. On the basis of the aforesaid, we present two novel GS/s DAC designs. The first is a 4-bit 10GS/s CS-DAC featuring INL 0.16LSB, DNL 0.12LSB, SFDR 23dBc across the Nyquist bandwidth, and power dissipation 30mW, for the cognitive ultra-wideband radio. These attributes are achieved primarily by the optimization of current sources based on our derivation of the relationship between the output impedance and INL, and by our proposed high-speed switch-driver circuit. Further, the CS-DAC embodies our proposed in-situ hardware efficient DPG that generates 4×10Gb/s test-data pattern to facilitate functional verification. The proposed CS-DAC achieves the highest Figure-of-Merit when benchmarked against state-of-the-art DACs. The second DAC design is a calibration-free/DEM-free 8-bit 2.4GS/s CS-DAC featuring INL ±0.097LSB (equivalent to ~11-bit accuracy), DNL −0.05/0.15LSB, SFDR 47.8dBc across the Nyquist bandwidth, and power dissipation 26.4mW. These attributes are achieved by our proposed distributed biasing scheme which largely decouples two critical trade-offs in the CS-DAC – the trade-off between the output impedance of the current-sources and their current mismatches, and that between the current mismatches and the delay differences. To simplify the CS-DAC measurements, we propose a custom in-situ 8×2.4Gb/s DPG. The proposed CS-DAC achieves the highest Figure-of-Merit when benchmarked against state-of-the-art DACs.