Hardware efficient algorithms and architectures for burst communications in cognitive radios

• Main Author: Syed Naveen Altaf Ahmed
• Other Authors: A. S. Madhukumar
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems; DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing; DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures; DRNTU::Engineering::Computer science and engineering::Hardware::Logic design
• Online Access: http://hdl.handle.net/10356/74185
• Institution: Nanyang Technological University

Wireless communications systems over the years have evolved to provide ubiquitous wireless connectivity for users who are increasingly mobile. More recently apart from the communication needs of the humans, data traffic originating and terminating from/to machines, machine to machine (M2M) communications, has increased. Furthermore, positioning and localization information have also been derived using the wireless communication signals. These diverse usage scenarios make the wireless modems necessary to operate in different channel environments meeting the ever increasing quality of service (QoS) requirements and with the decreasing availability of dedicated frequency spectrum. Burst communications with reconfigurable modems based on technologies such as Cognitive Radios (CR) and Cognitive Radio Networks (CRN) could satisfy these diverse systems requirements by transmitting information in short intervals, detecting the available frequency bands for transmission and accurately estimating the burst signal’s time-of-arrival at the receiver so that the receiver is synchronized for effective computation of the positioning information and demodulation of the transmitted data. For this purpose, there are many spectrum sensing, time of arrival and synchronization algorithms which have been proposed in literature. Most methods are based on covariance and/or correlation of the received signal with known features of the transmitted signal. However, since these algorithms operate on received signal samples, even before any receiver corrections such as carrier frequency offset or channel equalization are performed, they need to be robust against different impairments and also be hardware efficient for low complexity implementation and low power consumption. This thesis proposes low complexity schemes and architectures for spectrum sensing, time synchronization, fast acquisition and time of arrival estimation which address the issues of robustness and hardware efficient implementation for low power consumption. The proposed schemes take advantage of the pilot signals and repetitive preamble features which are part of the burst communication signals. The proposed algorithms are based on segmented processing of the received signal samples, processing only a derived signal or a single preamble out of the repetitive preambles. An analytical formulation is presented to explain how the proposed schemes are able to provide sufficient robustness and simplification of the hardware implementation. Further, performance of the proposed segmented processing schemes are evaluated through simulations over different propagation channel environments and comparisons with existing methods are presented. To evaluate the proposed segmented schemes in terms of implementation hardware complexity, FPGA synthesis is conducted and results are presented.