High-frequency clock generators

• Main Author: Lugan, Marshall Valiant
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/74632
• Institution: Nanyang Technological University

The project pertains to the design of critical building blocks of an RF Frequency Synthesizer for a low-power Bluetooth medical patch application. The critical building blocks are a Voltage Controlled Oscillator (VCO), a divide-by-2 circuit, and a Frequency Divider (FD). Their overall requirements are 1.1 V supply and <10mW power dissipation, and compliance to the Bluetooth standard including 2.4-2.48 GHz frequency band (Industrial-Scientific-Medical band), 79 channels, and <120 dBc/MHz phase-noise. The VCO is designed with the LC cross-coupled topology for its low phase-noise performance. Simulation results shows that the combined VCO and Divide-by-2 circuit achieves ~ 127 dBc/MHz phase-noise at 2.4 GHz output frequency. The divide-by-2 circuit is capable in generating four output signals with 0°, 90°, 180°, and 270° phase-shifts, thereby rendering it highly useful for different state-of-the-art transmitter architectures (that demand different amounts of phase-shifts). The FD has a simple architecture and is capable of dividing the 2.4 GHz-2.48 GHz input frequency by a range of numbers from 2402 to 2480 in order to comply with the 1 MHz channel spacing Bluetooth requirement. Simulation results show that the FD dissipates 0.32 mW. From simulations, the total power dissipation of the three building blocks is 7.7 mW. The Pulse Swallow Frequency Divider employs a proposed 2/3 Dual Modulus Prescaler architecture. The proposed architecture employs a D latch based on the Current Mode Logic to reduce the transistors count, and supports complementary logic operation. The Frequency Divider also employs a simple Program Counter with a chain of D flip-flop and an Asynchronous Swallow Counter.