Frequency compensation in an input folded cascode output buffered opamp

• Main Author: Phyo Wai Lin Kyaw@Lim Da Huang
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/74660
• Institution: Nanyang Technological University

Frequency compensation and power amplifier are the most significant and most used structures in every circuit design. The need for a large DC gain and a low power consumption in every device like handphones, speakers, mp3 etc. are a requirement for every designer. Frequency compensation for the closed loop system must be stable. For stability the phase-margin (PM) must be over 60°. The PMOS input folded cascode circuit operational transconductance amplifiers (OTA) give a large gain but is only able to drive a capacitive load. Therefore, the output stage must be designed so that the OTA is able to drive a small resistance load. Power amplifier is used in the output stage. However, there are different classes of output stage such as A, B and AB. Class AB is chosen for the output stage because it can give a rail-to-rail output system for a low input voltage amplifier, also has high power efficiency and less distortion. In this project, the whole design consists of the wide swing constant transconductance biasing circuit to make sure every transistor is in their conducting region, a PMOS input folded cascode circuit as an OTA and a push-pull class AB output stage. This designed circuit can achieve 82dB open loop gain that has a phase margin of 83.34°. The total harmonic distortion is minimized and the power supply rejection ration (PSRR) is 80dB. I have used Cadence Custom IC Design Tools based on 0.18μm CSM CMOS virtual software to achieve the design requirements for this project.