Multi-valued logic synthesis for Resistive Random Access Memory (RERAM) based in-memory computing

• Main Author: Surhonne Anmol Prakash
• Other Authors: Gwee Bah Hwee
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76071
• Institution: Nanyang Technological University

In-memory computing is a growing field of research which involves storing and processing of data at the memory. Resistive random access memory devices (RERAM) are among the class of memories which enable in-memory computing. RERAM devices are known to implement the material implication operation. It has been recently shown that these devices can be used to implement the multi-valued implication operator. Hence this work focuses on multi valued logic synthesis for in-memory computing using ReRam devices. The synthesis of multi-valued combinational functions is well-studied topic, albeit less compared to the synthesis of two-valued logic families. The synthesis of multivalued functions consists of bi-decomposition or functional decomposition of the given target function to obtain a multilevel network comprising of MIN and MAX gates. Synthesis tools, such as YADE and those based on Multi-valued decision diagrams make the implicit assumption regarding the availability of literals or CASE operator, while focusing on the optimization of the logic network solely based on the MIN and MAX gates. However, a literal cannot be assumed to exist as a primitive in a multivalued logic system and therefore, renders it difficult for one to directly apply the existing synthesis flows in practical settings. We address this important gap in MVL synthesis flows. Our target multi-valued logic is Łukasiewicz logic, which supports implication and negation operators. We derive literals and CASE operators using these primitives, and propose a heuristic algorithm to synthesize it automatically. Experimental studies on a wide range of benchmarks reveal that an average overhead of 216% in terms of number implication gates, along with 55% increase in the number of levels is encountered, in contrast to a synthesis flow that assumes existence of literals. Along with this, we also propose a method to synthesize circuits using binary-encoded decision diagrams. Experimental results on arithmetic circuits show a improvement of 25:9% levels and 4% gates.