Characterization of DPLL and ADC in the RF receiver chain

• Main Author: Sreyamsh, Megha
• Other Authors: Zhou Xing
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/76087
• Institution: Nanyang Technological University

The focus of this thesis is to know how to characterize and validate the DPLL and ADC blocks in the RF receiver chain, the different analysis to be done and different validation constraints to be considered. Considering this, all blocks like LNA, Mixer, DPLL, Mixer, ADC are validated under different simulations and under different voltages, temperature etc. Before getting into validation, a detailed study of DPLL and ADC blocks in RF receiver chain is done. The details of how the validation is carried out for all the boards is explained in this thesis report. The Analog to Digital converters at Intel are used for different purposes namely, accurate voltage/current measurements, calibration of different components of a firmware etc. the behavior of ADC is limited by several factors among which, supply voltages, temperature of system are critical. The thesis aims to meet the specification values of an 8-bit SAR ADC in all specified supply voltages and temperatures. The ADC is characterized by its offset error, gain error, integral non-linearity, differential non-linearity, signal-to-noise ratio, spurious free dynamic range and Effective number of bits. To ensure optimum behavior under worst scenarios, the characterization is performed for multiple corners i.e. fast, typical and slow. Using source meter, the ADC data is collected across three distinct temperatures and post processed using MATLAB. A phase Locked Loop (PLL) is broadly used in applications such as frequency synthesizing, frequency control, frequency and phase demodulation, phase modulation, data recovery, signal synchronization etc. The main application of PLL involves removing of jitter which is phase fluctuation on a signal of clock. It is basically a flip flop consisting of a phase detector for comparing phases of an input and an output signal, a low pass filter (LPF) for supplying a control signal in accordance with the signal supplied from phase detector, and a voltage controlled oscillator (VCO) for adjusting the output signal’s phase according to the control signal given from the loop filter so that there is synchronization between the input signal and the output signal. A PLL can be basically a receiver which can detect frequency related data and input signal’s phase of the accurately and generate an output error signal. Depending on this error signal it modifies the phase and frequency of the LO. A single IC can give a complete PLL block which can be used to generate stable frequencies and hence it is broadly used in modern electronic devices, with output frequency from a fraction of a hertz to many gigahertz. PLLs have huge applications ranging from radio and television, all communications (wireless, telecom, Datacom), all types of storage devices, noise cancellers, etc. In this thesis I will be covering basic operation of PLL, components of PLL, Types of PLL and their working, validation of different parameters of DPLL.