FPGA implementation of Kahan summation algorithm
In this project, Kahan Summation Algorithm, and an improved version of it, Kahan- Babuska Algorithm have been implemented in an FPGA platform to increase the accuracy in basic floating-point computation The Kahan Summation Algorithm is a method to add floating point numbers in a way to reduce the...
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| 主要作者: | |
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| 其他作者: | |
| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2018
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/76134 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In this project, Kahan Summation Algorithm, and an improved version of it, Kahan-
Babuska Algorithm have been implemented in an FPGA platform to increase the
accuracy in basic floating-point computation The Kahan Summation Algorithm is a
method to add floating point numbers in a way to reduce the accumulation of error.
The designs are configurable to sum to 100 floating point numbers. There are two
implementations of the Kahan Summation Algorithm design, a purely blocking mode,
and a hybrid mode with pipelining. The Kahan-Babuska algorithm is implemented in
blocking mode. The designs have also been compared with each other, along with
software implementations to study the effectiveness of the implementation. |
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