Design of the asynchronous dynamic reference ADC
An 8 bits asynchronous dynamic reference analog to digital converter, ADC is introduced in this paper. The proposed ADC is a type of ADC that consists of N number of comparator/s for N number of bit/s and not governed by any clock signal. The whole design of the proposed ADC consists of 8 comparator...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/76267 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | An 8 bits asynchronous dynamic reference analog to digital converter, ADC is introduced in this paper. The proposed ADC is a type of ADC that consists of N number of comparator/s for N number of bit/s and not governed by any clock signal. The whole design of the proposed ADC consists of 8 comparators, 7 current steering DACs and wide swing constant-transconductance bias circuit.
The proposed ADC is implemented with the aids of Cadence Virtuoso® Schematic Editor and Cadence Virtuoso® Analog Design Environment (ADE) with process technology of CHRT 0.18 µm. It is designed to convert an analog signal, which ranges from 0 V to 1 V, to an 8 bits digital signal.
The proposed ADC works under 1.8 V power supply and sampling frequency of 4 MHz. Under such specification, the ADC acquires 7.722 effective number of bits (ENOB), and power dissipated of 5.034 mWatt. In conclusion, performance of the ADC is measured by figure-of-merit, FOM of 5.96 pJ. |
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