Timing mismatch calibration for time- interleaved ADC

The project displays an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converter. Digital adaptive timing mismatch estimation and digital derivative based correction is combined to attain lower cost and better correction of timing mismatch. An expression...

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Bibliographic Details
Main Author:	Tan, Clarice Wen Ying
Other Authors:	Chang Joseph Sylvester
Format:	Final Year Project
Language:	English
Published:	2019
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	http://hdl.handle.net/10356/77468
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-77468
record_format	dspace
spelling	sg-ntu-dr.10356-774682023-07-07T15:57:09Z Timing mismatch calibration for time- interleaved ADC Tan, Clarice Wen Ying Chang Joseph Sylvester School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The project displays an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converter. Digital adaptive timing mismatch estimation and digital derivative based correction is combined to attain lower cost and better correction of timing mismatch. An expression for signal to noise and distortion ratio (SNDR) of four-channel after correction. Simulation result will show signal of various stages of the project (sampling by each ADC channels, the signal after derivative filter, timing mismatch estimator, and corrected signal). Results also confirm SNDR characteristic of vin, sampled and corrected signals. Bachelor of Engineering (Electrical and Electronic Engineering) 2019-05-29T07:06:43Z 2019-05-29T07:06:43Z 2019 Final Year Project (FYP) http://hdl.handle.net/10356/77468 en Nanyang Technological University 59 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Tan, Clarice Wen Ying Timing mismatch calibration for time- interleaved ADC
description	The project displays an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converter. Digital adaptive timing mismatch estimation and digital derivative based correction is combined to attain lower cost and better correction of timing mismatch. An expression for signal to noise and distortion ratio (SNDR) of four-channel after correction. Simulation result will show signal of various stages of the project (sampling by each ADC channels, the signal after derivative filter, timing mismatch estimator, and corrected signal). Results also confirm SNDR characteristic of vin, sampled and corrected signals.
author2	Chang Joseph Sylvester
author_facet	Chang Joseph Sylvester Tan, Clarice Wen Ying
format	Final Year Project
author	Tan, Clarice Wen Ying
author_sort	Tan, Clarice Wen Ying
title	Timing mismatch calibration for time- interleaved ADC
title_short	Timing mismatch calibration for time- interleaved ADC
title_full	Timing mismatch calibration for time- interleaved ADC
title_fullStr	Timing mismatch calibration for time- interleaved ADC
title_full_unstemmed	Timing mismatch calibration for time- interleaved ADC
title_sort	timing mismatch calibration for time- interleaved adc
publishDate	2019
url	http://hdl.handle.net/10356/77468
_version_	1772828640530137088

Timing mismatch calibration for time- interleaved ADC

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