Implementation of cryptography algorithm on hardware platform

• Main Author: Tam, Zi Hao
• Other Authors: Ho Duan Juat
• Format: Final Year Project
• Language: English
• Published: 2019
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/78188
• Institution: Nanyang Technological University

Development of Cyber-Physical System due to the emerging of the “Industrial 4.0” concept had revolutionized the traditional IoT devices. Secure communications based on encryption between devices are crucial in maintaining the integrity of the system. In this project, an FPGA solution of high performance ECC based cryptosystem is implemented. The cryptosystem operating on the binary field using a bit length of 163 bits. ECC scheme domain parameter of B-163 defined in [1] is used in this project. The scalar multiplication entity used in the key generation process entity utilized 11964 LUT / slices and has a maximum frequency of 200MHz. The operation required 14581 cycles and have a time delay of 72.905 μs for a single operation. It can perform multiplication or generate 13716 keys per second. 64.7 times faster than the software implementation reported in [2]. Next in the demonstration of encryption and decryption utilizing the designed scalar multiplication entity. Due to the hardness in place and route, it is reported running on a 180MHz clock and required around 32104 cycles to establishing the secure communication channel. The transmission of the cipher can only be started after 178.35μs time. Therefore, the implemented elliptic curve cryptographic processor is highly suitable to be deployed in an application that required high throughput rate for engaging a high volume of communication requests from different parties.