K-locked-loop and its application in time mode ADC

• Main Authors: Hor, Hon Cheong, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/79867; http://hdl.handle.net/10220/6283; http://www.isic2009.org/; http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403964
• Institution: Nanyang Technological University

VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. A 9-bit, 0.5MS/s time mode ADC has been modeled using SIMULINK tool in Matlab. Some of the circuits are simulated using Spectre simulator tool in Cadence using the 0.18μm CSM process, and the simulation result is back annotated to SIMULINK model to make the behavioral modeling more comprehensive and accurate.