Hybrid-mode SRAM sense amplifiers : new approach on transistor sizing
A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have prov...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/79962 http://hdl.handle.net/10220/6260 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have proved that the new Sense Amplifier provides both high-speed and low-power properties, with its delay and power reduced to 25.8% and 37.6% of those of the best prior art. It also offers a much better read-effectiveness and robustness against the bit- and data-line capacitances as well as VDD variations. Furthermore, the new Sense Amplifier is able to tolerate a large difference between the parasitic capacitances associated with the complementary DLs. It can operate down to a supply voltage of 0.9 V, the lowest reported for a 0.18 µm CMOS process. A modified cross-coupled amplifier is also introduced, allowing the Sense Amplifier to operate down to 0.55 V. |
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