GraphMMU: Memory Management Unit for Sparse Graph Accelerators

• Main Authors: Han, Jianglei, Kapre, Nachiket, Bean, Andrew, Moorthy, Pradeep, Siddhartha
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: Computer Science and Engineering
• Online Access: https://hdl.handle.net/10356/81201; http://hdl.handle.net/10220/39176
• Institution: Nanyang Technological University

Memory management units that use low-level AXI descriptor chains to hold irregular graph-oriented access sequences can help improve DRAM memory throughput of graph algorithms by almost an order of magnitude. For the Xilinx Zed board, we explore and compare the memory throughputs achievable when usin...