Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation

This paper proposes a space vector modulation based dc-link capacitor voltage balancing technique for a five-level multiple-pole multilevel diode-clamped (M2DCI) inverter. The new five-level inverter contains lesser number of clamping diodes compared to the conventional five-level diode-clamped inve...

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Main Authors: Raj, Pinkymol Harikrishna, Maswood, Ali Iftekhar, Ooi, Gabriel Heo Peng, Dehghani Tafti, Hossein
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2016
Subjects:
SVM
Online Access:https://hdl.handle.net/10356/82260
http://hdl.handle.net/10220/39894
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-822602021-01-08T07:28:38Z Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation Raj, Pinkymol Harikrishna Maswood, Ali Iftekhar Ooi, Gabriel Heo Peng Dehghani Tafti, Hossein School of Electrical and Electronic Engineering 2015 IEEE International Conference on Electron Devices and Solid-State Circuits Energy Research Institute @ NTU (ERI@N) Multilevel inverter SVM Five-level NPC inverter Neutral point potential Active balancing circuit This paper proposes a space vector modulation based dc-link capacitor voltage balancing technique for a five-level multiple-pole multilevel diode-clamped (M2DCI) inverter. The new five-level inverter contains lesser number of clamping diodes compared to the conventional five-level diode-clamped inverter (DCI) topology and does not require any extra balancing circuits to maintain balanced voltages across the four dc-link capacitors. The effect of load power factor and modulation indices on voltage balancing strategy has been studied, and the stability region for five-level M2DCI is determined based on investigation done in the Matlab/Simulink?? and PSIM environment during balanced, unbalanced and distorted load conditions. The proposed reduced device topology with SVM technique, which self balances the dc-link capacitors can be very attractive for reactive power control in a grid connected environment. Accepted version 2016-02-01T02:32:45Z 2019-12-06T14:51:58Z 2016-02-01T02:32:45Z 2019-12-06T14:51:58Z 2015 Conference Paper Raj, P. H., Maswood, A. I., Ooi, G. H. P., & Dehghani Tafti, H. (2015). Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation. 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, 57-60. https://hdl.handle.net/10356/82260 http://hdl.handle.net/10220/39894 10.1109/EDSSC.2015.7285048 en © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/EDSSC.2015.7285048]. 5 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Multilevel inverter
SVM
Five-level NPC inverter
Neutral point potential
Active balancing circuit
spellingShingle Multilevel inverter
SVM
Five-level NPC inverter
Neutral point potential
Active balancing circuit
Raj, Pinkymol Harikrishna
Maswood, Ali Iftekhar
Ooi, Gabriel Heo Peng
Dehghani Tafti, Hossein
Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
description This paper proposes a space vector modulation based dc-link capacitor voltage balancing technique for a five-level multiple-pole multilevel diode-clamped (M2DCI) inverter. The new five-level inverter contains lesser number of clamping diodes compared to the conventional five-level diode-clamped inverter (DCI) topology and does not require any extra balancing circuits to maintain balanced voltages across the four dc-link capacitors. The effect of load power factor and modulation indices on voltage balancing strategy has been studied, and the stability region for five-level M2DCI is determined based on investigation done in the Matlab/Simulink?? and PSIM environment during balanced, unbalanced and distorted load conditions. The proposed reduced device topology with SVM technique, which self balances the dc-link capacitors can be very attractive for reactive power control in a grid connected environment.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Raj, Pinkymol Harikrishna
Maswood, Ali Iftekhar
Ooi, Gabriel Heo Peng
Dehghani Tafti, Hossein
format Conference or Workshop Item
author Raj, Pinkymol Harikrishna
Maswood, Ali Iftekhar
Ooi, Gabriel Heo Peng
Dehghani Tafti, Hossein
author_sort Raj, Pinkymol Harikrishna
title Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
title_short Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
title_full Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
title_fullStr Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
title_full_unstemmed Five-Level Multiple-Pole Mutlilevel Diode-Clamped Inverter Scheme for Reactive Power Compensation
title_sort five-level multiple-pole mutlilevel diode-clamped inverter scheme for reactive power compensation
publishDate 2016
url https://hdl.handle.net/10356/82260
http://hdl.handle.net/10220/39894
_version_ 1688665475648585728