Exploiting FPGA Block Memories for Protected Cryptographic Implementations

Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used i...

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Main Authors: Bhasin, Shivam, Danger, Jean-Luc, Guilley, Sylvain, He, Wei
Other Authors: Temasek Laboratories
Format: Article
Language:English
Published: 2016
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Online Access:https://hdl.handle.net/10356/83419
http://hdl.handle.net/10220/41430
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-834192020-09-26T22:19:06Z Exploiting FPGA Block Memories for Protected Cryptographic Implementations Bhasin, Shivam Danger, Jean-Luc Guilley, Sylvain He, Wei Temasek Laboratories FPGA Side-Channel Analysis Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security. Accepted version 2016-09-06T08:51:04Z 2019-12-06T15:22:04Z 2016-09-06T08:51:04Z 2019-12-06T15:22:04Z 2015 Journal Article Bhasin, S., Danger, J.-L., Guilley, S., & He, W. (2015). Exploiting FPGA Block Memories for Protected Cryptographic Implementations. ACM Transactions on Reconfigurable Technology and Systems, 8(3), 1-16. 1936-7406 https://hdl.handle.net/10356/83419 http://hdl.handle.net/10220/41430 10.1145/2629552 en ACM Transactions on Reconfigurable Technology and Systems © 2015 Association for Computing Machinery (ACM). This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM). It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1145/2629552]. 16 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic FPGA
Side-Channel Analysis
spellingShingle FPGA
Side-Channel Analysis
Bhasin, Shivam
Danger, Jean-Luc
Guilley, Sylvain
He, Wei
Exploiting FPGA Block Memories for Protected Cryptographic Implementations
description Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.
author2 Temasek Laboratories
author_facet Temasek Laboratories
Bhasin, Shivam
Danger, Jean-Luc
Guilley, Sylvain
He, Wei
format Article
author Bhasin, Shivam
Danger, Jean-Luc
Guilley, Sylvain
He, Wei
author_sort Bhasin, Shivam
title Exploiting FPGA Block Memories for Protected Cryptographic Implementations
title_short Exploiting FPGA Block Memories for Protected Cryptographic Implementations
title_full Exploiting FPGA Block Memories for Protected Cryptographic Implementations
title_fullStr Exploiting FPGA Block Memories for Protected Cryptographic Implementations
title_full_unstemmed Exploiting FPGA Block Memories for Protected Cryptographic Implementations
title_sort exploiting fpga block memories for protected cryptographic implementations
publishDate 2016
url https://hdl.handle.net/10356/83419
http://hdl.handle.net/10220/41430
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