Distributed In-Memory Computing on Binary RRAM Crossbar

• Main Authors: Ni, Leibin, Huang, Hantao, Liu, Zichuan, Joshi, Rajiv V., Yu, Hao
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2017
• Subjects: RRAM crossbar; Hardware accelerator
• Online Access: https://hdl.handle.net/10356/85628; http://hdl.handle.net/10220/43796
• Institution: Nanyang Technological University

The recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM crossbar--based computing is mainly assumed as a multilevel analog computing, whose result is sensitive to process nonuniformity as well as additional overhead from AD-conversion and I/O. In this article, we explore the matrix-vector multiplication accelerator on a binary RRAM crossbar with adaptive 1-bit-comparator--based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with the according control protocol. Both memory array and logic accelerator are implemented on the binary RRAM crossbar, where the logic-memory pair can be distributed with the control bus protocol. Experimental results have shown that compared to the analog RRAM crossbar, the proposed binary RRAM crossbar can achieve significant area savings with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in neural network--based machine learning such that the overall training and testing time can be both reduced. In addition, large energy savings can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.