APA引文

Gu, C., Ang, D. S., Gao, Y., Gu, R., Zhao, Z., Zhu, C., & Engineering, S. o. E. a. E. (2018). A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET.

Chicago Style Citation

Gu, Chenjie, Diing Shenp Ang, Yuan Gao, Renyuan Gu, Ziqi Zhao, Chao Zhu, and School of Electrical and Electronic Engineering. A Vacancy-interstitial Defect Pair Model for Positive-bias Temperature Stress-induced Electron Trapping Transformation in the High-κ Gate N-MOSFET. 2018.

MLA引文

Gu, Chenjie, et al. A Vacancy-interstitial Defect Pair Model for Positive-bias Temperature Stress-induced Electron Trapping Transformation in the High-κ Gate N-MOSFET. 2018.