Improving main memory hash joins on Intel Xeon Phi processors

• Main Authors: Jha, Saurabh, He, Bingsheng, Lu, Mian, Cheng, Xuntao, Huynh, Huynh Phung
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Computer science and engineering; Many Integrated Core; Xeon Phi
• Online Access: https://hdl.handle.net/10356/87784; http://hdl.handle.net/10220/46835
• Institution: Nanyang Technological University

Modern processor technologies have driven new designs and implementations in main-memory hash joins. Recently, Intel Many Integrated Core (MIC) co-processors (commonly known as Xeon Phi) embrace emerging x86 single-chip many-core techniques. Compared with contemporary multi-core CPUs, Xeon Phi has quite different architectural features: wider SIMD instructions, many cores and hardware contexts, as well as lower-frequency in-order cores. In this paper, we experimentally revisit the state-of-the-art hash join algorithms on Xeon Phi co-processors. In particular, we study two camps of hash join algorithms: hardware-conscious ones that advocate careful tailoring of the join algorithms to underlying hardware architectures and hardware-oblivious ones that omit such careful tailoring. For each camp, we study the impact of architectural features and software optimizations on Xeon Phi in comparison with results on multi-core CPUs. Our experiments show two major findings on Xeon Phi, which are quantitatively different from those on multi-core CPUs. First, the impact of architectural features and software optimizations has quite different behavior on Xeon Phi in comparison with those on the CPU, which calls for new optimization and tuning on Xeon Phi. Second, hardware oblivious algorithms can outperform hardware conscious algorithms on a wide parameter window. These two findings further shed light on the design and implementation of query processing on new-generation single-chip many-core technologies.