Low-power high-performance SAR ADC with redundancy and digital error-correction

• Main Author: Sharma, Sunny
• Other Authors: Boon Chirn Chye
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/89791; http://hdl.handle.net/10220/46396
• Institution: Nanyang Technological University

The demands for data converters have soared in the last decade with the boom in consumer electronics, smart devices, autonomous vehicles, and automotive segments. The current trend among Nyquist-rate data converters, for example successive approximation register (SAR) analog-to-digital converters (ADC), tends towards high speeds and medium-to-high resolution. Applications such as vehicle-to-everything (V2X) communication, wireless internet of things, test systems, etc., benefit from high-speed and high resolution ADCs. An in-depth analysis of data converter trends, and current state-of-the-art SAR ADCs are discussed. The topics discussed include data converters using binary and non-binary redundancy techniques, digital error correction schemes, DAC switching schemes, and associated hardware overheads. This thesis focuses on six important contributions to high speed and medium resolution SAR ADC research. The first one is the introduction of binary-scaled redundancy embedded in the conventional capacitive DAC (CDAC), and the second is optimizing the use of redundancy by introducing a new CDAC switching scheme. The third contribution introduces a simple “bit overlap and add” digital error correction-technique for a 10-bit SAR ADC. Multiple erroneous decisions can be corrected over nine conversion cycles, independent of where the erroneous conversion cycle occurred. The implementation of the technique requires no additional conversion cycles to obtain a 10-bit resolution. Fourth, this thesis introduces a new area-efficient switching scheme for a multi-bit per cycle SAR ADC. The proposed constant common-mode fractional reference voltage (CCM-FRV) switching scheme offers a 50% area reduction of each CDAC used when compared to a conventional switching scheme [1] modified to implement a similar redundancy and error correction concept. The implementation of the CCM-FRV switching scheme requires no special arithmetic units or additional hardware overheads to compute the DAC switching pattern, thus eliminating any speed bottlenecks due to logic delay. The fifth contribution introduces a low-energy and chip-area-efficient switching scheme for a 1.5-bit/cycle SAR ADC with digital error-correction. The proposed switching scheme reduces CDAC switching energy by 88.55%, along with a 75% CDAC area reduction when compared to a conventional switching scheme [1] implementing a similar 1.5-bit/cycle conversion. Finally, a “more than Moore” design and fabrication methodology is explored to compare III-V compound semiconductors (CS) and CMOS sampling switch performance. The first four contributions are implemented using a 65 nm 1P9M mixed-signal RF CMOS technology. The test chip occupies a 0.038 mm2 chip area and consumes 4.06 mW from a 1.2 V power supply. The prototype achieves Nyquist SNDR of 57.81 dB and an ENOB of 9.31 at 150 MS/s. The Walden figure of merit (FoM) is 42.6 fJ/conversion-step. The sixth contribution implements an on-chip fully integrated SAR ADC with III-V CS (i.e., InGaAs) sampling switch and remaining circuits in CMOS technology. The 6-bit 125 MSps SAR ADC occupies a 0.0225 mm2 chip area, achieves a post-layout simulated peak SNDR of 35.56 dB/35.98 dB and an SFDR of 48.7 dB/53.17 dB for ADCs using a CMOS/InGaAs sampling switch. The ADC using an InGaAs sampling switch has a better SFDR performance by 4.47 dB when compared to an ADC using a CMOS sampling switch for the given technology nodes.