Speed and energy optimized quasi-delay-insensitive block carry lookahead adder

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster a...

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Main Authors: Mastorakis, N. E., Balasubramanian, Padmanabhan, Maskell, Douglas Leslie
Other Authors: Ma, Jun
Format: Article
Language:English
Published: 2019
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Online Access:https://hdl.handle.net/10356/90051
http://hdl.handle.net/10220/49393
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-900512020-03-07T11:49:00Z Speed and energy optimized quasi-delay-insensitive block carry lookahead adder Mastorakis, N. E. Balasubramanian, Padmanabhan Maskell, Douglas Leslie Ma, Jun School of Computer Science and Engineering Engineering::Computer science and engineering Logic Circuits Data Processing We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology. MOE (Min. of Education, S’pore) Published version 2019-07-17T02:38:24Z 2019-12-06T17:39:36Z 2019-07-17T02:38:24Z 2019-12-06T17:39:36Z 2019 Journal Article Balasubramanian, P., Maskell, D. L., & Mastorakis, N. E. (2019). Speed and energy optimized quasi-delay-insensitive block carry lookahead adder. PLoS ONE, 14(6), e0218347-. doi:10.1371/journal.pone.0218347 https://hdl.handle.net/10356/90051 http://hdl.handle.net/10220/49393 10.1371/journal.pone.0218347 en PLoS ONE © 2019 Balasubramanian et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. 27 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Engineering::Computer science and engineering
Logic Circuits
Data Processing
spellingShingle Engineering::Computer science and engineering
Logic Circuits
Data Processing
Mastorakis, N. E.
Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
description We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.
author2 Ma, Jun
author_facet Ma, Jun
Mastorakis, N. E.
Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
format Article
author Mastorakis, N. E.
Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
author_sort Mastorakis, N. E.
title Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
title_short Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
title_full Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
title_fullStr Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
title_full_unstemmed Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
title_sort speed and energy optimized quasi-delay-insensitive block carry lookahead adder
publishDate 2019
url https://hdl.handle.net/10356/90051
http://hdl.handle.net/10220/49393
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