Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip

Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these core...

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Main Authors: Liu, Weichen, Yang, Lei, Jiang, Weiwen, Feng, Liang, Guan, Nan, Zhang, Wei, Dutt, Nikil
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2019
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Online Access:https://hdl.handle.net/10356/90107
http://hdl.handle.net/10220/48373
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-901072023-12-06T07:37:03Z Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip Liu, Weichen Yang, Lei Jiang, Weiwen Feng, Liang Guan, Nan Zhang, Wei Dutt, Nikil School of Computer Science and Engineering Reconfigurable NoC Task Mapping DRNTU::Engineering::Computer science and engineering Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap, on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs. 2019-05-27T04:02:14Z 2019-12-06T17:40:49Z 2019-05-27T04:02:14Z 2019-12-06T17:40:49Z 2018 Journal Article Liu, W., Yang, L., Jiang, W., Feng, L., Guan, N., Zhang, W., & Dutt, N. (2018). Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip. IEEE Transactions on Computers, 67(12), 1818-1834. doi:10.1109/TC.2018.2844365 0018-9340 https://hdl.handle.net/10356/90107 http://hdl.handle.net/10220/48373 10.1109/TC.2018.2844365 en IEEE Transactions on Computers IEEE Transactions on Computers doi:10.21979/N9/NOZOQ9 © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TC.2018.2844365. 16 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Reconfigurable NoC
Task Mapping
DRNTU::Engineering::Computer science and engineering
spellingShingle Reconfigurable NoC
Task Mapping
DRNTU::Engineering::Computer science and engineering
Liu, Weichen
Yang, Lei
Jiang, Weiwen
Feng, Liang
Guan, Nan
Zhang, Wei
Dutt, Nikil
Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
description Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap, on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Liu, Weichen
Yang, Lei
Jiang, Weiwen
Feng, Liang
Guan, Nan
Zhang, Wei
Dutt, Nikil
format Article
author Liu, Weichen
Yang, Lei
Jiang, Weiwen
Feng, Liang
Guan, Nan
Zhang, Wei
Dutt, Nikil
author_sort Liu, Weichen
title Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
title_short Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
title_full Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
title_fullStr Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
title_full_unstemmed Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
title_sort thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
publishDate 2019
url https://hdl.handle.net/10356/90107
http://hdl.handle.net/10220/48373
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