Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors

• Main Authors: Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/90560; http://hdl.handle.net/10220/6004
• Institution: Nanyang Technological University

Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1–1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features 37% lower energy per FFT/IFFT computation than the sync approach but with 10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35- m CMOS process) can be operated at 1.0 V and dissipates 93 nJ.