An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power

• Main Authors: Jaya, Gibran Limi, Chan, Pak Kwong
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: https://hdl.handle.net/10356/91706; http://hdl.handle.net/10220/6340; http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5403946&queryText%3DAn+Ultra+Low-Power+CMOS+EMG+Amplifier+with+High+Efficiency+in+Operation+Frequency+per+Power%26openedRefinements%3D*%26searchField%3DSearch+All; http://www.isic2009.org/

A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the op-amp for reducing power driving requirement. The amplifier is designed using CSM 1.8V 0.18μm triple-well CMOS process technology and simulated using realistic BSIM3 models. The amplifier dissipates only 15.14μW at a dual power supply of ±0.9V. It has has a gain of 40dB at dc and 38.5dB at 3.2kHz. The estimated passband inputreferred noise is 2.08μVrms.