An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power

An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power

A new ultra low-power CMOS Electromyograph...

Full description

Saved in:
Bibliographic Details
Main Authors: Jaya, Gibran Limi, Chan, Pak Kwong
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2010
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:https://hdl.handle.net/10356/91706
http://hdl.handle.net/10220/6340
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5403946&queryText%3DAn+Ultra+Low-Power+CMOS+EMG+Amplifier+with+High+Efficiency+in+Operation+Frequency+per+Power%26openedRefinements%3D*%26searchField%3DSearch+All
http://www.isic2009.org/
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-91706
record_format dspace
spelling sg-ntu-dr.10356-917062019-12-06T18:10:30Z An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power Jaya, Gibran Limi Chan, Pak Kwong School of Electrical and Electronic Engineering IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore) DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the op-amp for reducing power driving requirement. The amplifier is designed using CSM 1.8V 0.18μm triple-well CMOS process technology and simulated using realistic BSIM3 models. The amplifier dissipates only 15.14μW at a dual power supply of ±0.9V. It has has a gain of 40dB at dc and 38.5dB at 3.2kHz. The estimated passband inputreferred noise is 2.08μVrms. Published version 2010-08-20T08:39:05Z 2019-12-06T18:10:30Z 2010-08-20T08:39:05Z 2019-12-06T18:10:30Z 2009 2009 Conference Paper Jaya, G. L., & Chan, P. K. (2009). An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power. In proceedings of the 12th International Symposium on Integrated Circuits: Singapore, (pp.433-436). https://hdl.handle.net/10356/91706 http://hdl.handle.net/10220/6340 http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5403946&queryText%3DAn+Ultra+Low-Power+CMOS+EMG+Amplifier+with+High+Efficiency+in+Operation+Frequency+per+Power%26openedRefinements%3D*%26searchField%3DSearch+All http://www.isic2009.org/ en © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Jaya, Gibran Limi
Chan, Pak Kwong
An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Jaya, Gibran Limi
Chan, Pak Kwong
format Conference or Workshop Item
author Jaya, Gibran Limi
Chan, Pak Kwong
author_sort Jaya, Gibran Limi
title An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
title_short An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
title_full An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
title_fullStr An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
title_full_unstemmed An ultra low-power CMOS EMG amplifier with high efficiency in operation frequency per power
title_sort ultra low-power cmos emg amplifier with high efficiency in operation frequency per power
publishDate 2010
url https://hdl.handle.net/10356/91706
http://hdl.handle.net/10220/6340
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5403946&queryText%3DAn+Ultra+Low-Power+CMOS+EMG+Amplifier+with+High+Efficiency+in+Operation+Frequency+per+Power%26openedRefinements%3D*%26searchField%3DSearch+All
http://www.isic2009.org/
_version_ 1681049314009284608
description A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the op-amp for reducing power driving requirement. The amplifier is designed using CSM 1.8V 0.18μm triple-well CMOS process technology and simulated using realistic BSIM3 models. The amplifier dissipates only 15.14μW at a dual power supply of ±0.9V. It has has a gain of 40dB at dc and 38.5dB at 3.2kHz. The estimated passband inputreferred noise is 2.08μVrms.

Similar Items