A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout
A new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1 noise and offset...
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| Main Authors: | , |
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| 格式: | Article |
| 語言: | English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/91707 http://hdl.handle.net/10220/4561 |
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| 總結: | A new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects
on crosstalk, gain loss, 1 noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with
4 TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8- m CMOS process.
Index Terms—Crosstalk, equalizers, integrated circuit, layout,
switched-capacitor (SC) circuit, time-multiplexed (TM) circuit. |
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