A new redundant binary Booth encoding for fast 2^n-bit multiplier design

The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is...

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Main Authors: He, Yajuan, Chang, Chip Hong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2010
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Online Access:https://hdl.handle.net/10356/91940
http://hdl.handle.net/10220/6242
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-919402020-03-07T14:02:37Z A new redundant binary Booth encoding for fast 2^n-bit multiplier design He, Yajuan Chang, Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18- m standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b. Published version 2010-04-30T07:19:25Z 2019-12-06T18:14:33Z 2010-04-30T07:19:25Z 2019-12-06T18:14:33Z 2009 2009 Journal Article © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 1549-8328 https://hdl.handle.net/10356/91940 http://hdl.handle.net/10220/6242 10.1109/TCSI.2008.2008503 en IEEE transactions on circuits and systems—I He, Y., & Chang, C. H. (2009). New Redundant Binary Booth Encoding for Fast 2^n-bit Multiplier Design. IEEE Transactions On Circuits And Systems—I. 56(6), 1192-1201. 10 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
He, Yajuan
Chang, Chip Hong
A new redundant binary Booth encoding for fast 2^n-bit multiplier design
description The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18- m standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
He, Yajuan
Chang, Chip Hong
format Article
author He, Yajuan
Chang, Chip Hong
author_sort He, Yajuan
title A new redundant binary Booth encoding for fast 2^n-bit multiplier design
title_short A new redundant binary Booth encoding for fast 2^n-bit multiplier design
title_full A new redundant binary Booth encoding for fast 2^n-bit multiplier design
title_fullStr A new redundant binary Booth encoding for fast 2^n-bit multiplier design
title_full_unstemmed A new redundant binary Booth encoding for fast 2^n-bit multiplier design
title_sort new redundant binary booth encoding for fast 2^n-bit multiplier design
publishDate 2010
url https://hdl.handle.net/10356/91940
http://hdl.handle.net/10220/6242
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