IP watermarking using incremental technology mapping at logic synthesis level

• المؤلفون الرئيسيون: Cui, Aijiao, Chang, Chip Hong, Tahar, Sofiène
• مؤلفون آخرون: School of Electrical and Electronic Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2010
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/93106; http://hdl.handle.net/10220/6259

This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainabili...