Using monterey phoenix to formalize and verify system architectures

Modeling and analyzing software architectures are useful for helping to understand the system structures and facilitate proper implementation of user requirements. Despite its importance in the software engineering practice, the lack of formal description and verification support hinders the develop...

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Main Authors: Zhang, Jiexin, Liu, Yang, Auguston, Mikhail, Sun, Jun, Dong, Jin Song
Other Authors: School of Computer Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Online Access:https://hdl.handle.net/10356/96488
http://hdl.handle.net/10220/12898
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-964882020-05-28T07:41:40Z Using monterey phoenix to formalize and verify system architectures Zhang, Jiexin Liu, Yang Auguston, Mikhail Sun, Jun Dong, Jin Song School of Computer Engineering Asia-Pacific Software Engineering Conference (19th : 2012 : Hong Kong, China) Modeling and analyzing software architectures are useful for helping to understand the system structures and facilitate proper implementation of user requirements. Despite its importance in the software engineering practice, the lack of formal description and verification support hinders the development of quality architectural models. In this work, we develop an approach for modeling and verifying software architectures specified using Monterey Phoenix (MP) architecture description language. Firstly, we formalize the syntax and operational semantics for MP. This language is capable of modeling system and environment behaviors based on event traces, as well as supporting different architecture composition operations and views. Secondly, a dedicated model checker for MP is developed based on PAT verification framework. Finally, several case studies are presented to evaluate the usability and effectiveness of our approach. 2013-08-02T06:01:25Z 2019-12-06T19:31:22Z 2013-08-02T06:01:25Z 2019-12-06T19:31:22Z 2012 2012 Conference Paper https://hdl.handle.net/10356/96488 http://hdl.handle.net/10220/12898 10.1109/APSEC.2012.60 en
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
description Modeling and analyzing software architectures are useful for helping to understand the system structures and facilitate proper implementation of user requirements. Despite its importance in the software engineering practice, the lack of formal description and verification support hinders the development of quality architectural models. In this work, we develop an approach for modeling and verifying software architectures specified using Monterey Phoenix (MP) architecture description language. Firstly, we formalize the syntax and operational semantics for MP. This language is capable of modeling system and environment behaviors based on event traces, as well as supporting different architecture composition operations and views. Secondly, a dedicated model checker for MP is developed based on PAT verification framework. Finally, several case studies are presented to evaluate the usability and effectiveness of our approach.
author2 School of Computer Engineering
author_facet School of Computer Engineering
Zhang, Jiexin
Liu, Yang
Auguston, Mikhail
Sun, Jun
Dong, Jin Song
format Conference or Workshop Item
author Zhang, Jiexin
Liu, Yang
Auguston, Mikhail
Sun, Jun
Dong, Jin Song
spellingShingle Zhang, Jiexin
Liu, Yang
Auguston, Mikhail
Sun, Jun
Dong, Jin Song
Using monterey phoenix to formalize and verify system architectures
author_sort Zhang, Jiexin
title Using monterey phoenix to formalize and verify system architectures
title_short Using monterey phoenix to formalize and verify system architectures
title_full Using monterey phoenix to formalize and verify system architectures
title_fullStr Using monterey phoenix to formalize and verify system architectures
title_full_unstemmed Using monterey phoenix to formalize and verify system architectures
title_sort using monterey phoenix to formalize and verify system architectures
publishDate 2013
url https://hdl.handle.net/10356/96488
http://hdl.handle.net/10220/12898
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