A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
Optical network-on-chip (ONoC) can be used as the communication backbone for high performance chip multiprocessors (CMPs). Fat tree based ONoC shows high throughput, small delay and low power consumption. However, the traditional floorplan design of fat tree based ONoC has a large number of waveguid...
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| Main Authors: | , , , , , , , , |
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| 其他作者: | |
| 格式: | Conference or Workshop Item |
| 語言: | English |
| 出版: |
2013
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/97799 http://hdl.handle.net/10220/12163 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Optical network-on-chip (ONoC) can be used as the communication backbone for high performance chip multiprocessors (CMPs). Fat tree based ONoC shows high throughput, small delay and low power consumption. However, the traditional floorplan design of fat tree based ONoC has a large number of waveguide crossings because of the fat tree topology. In this paper, we present an optimized floorplan with the least number of waveguide crossings that has been reported. The average number of waveguide crossings per optical path in the optimized floorplan is 87% less than that in traditional floorplan for a 64-core CMP. We also find the optimal aspect ratio of cores to minimize the end-to-end delay. These work could help to ease the physical implementation of fat tree based ONoC for CMP. |
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