A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip
Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communicatio...
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sg-ntu-dr.10356-979922020-05-28T07:19:24Z A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip Ye, Yaoyao Xu, Jiang Wu, Xiaowen Zhang, Wei Liu, Weichen Nikdast, Mahdi School of Computer Engineering DRNTU::Engineering::Computer science and engineering Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC. 2013-07-25T07:59:00Z 2019-12-06T19:49:07Z 2013-07-25T07:59:00Z 2019-12-06T19:49:07Z 2012 2012 Journal Article Ye, Y., Xu, J., Wu, X., Zhang, W., Liu, W., & Nikdast, M. (2012). A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip. ACM Journal on Emerging Technologies in Computing Systems, 8(1). 1550-4832 https://hdl.handle.net/10356/97992 http://hdl.handle.net/10220/12296 10.1145/2093145.2093150 en ACM journal on emerging technologies in computing systems © 2012 ACM. |
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DRNTU::Engineering::Computer science and engineering Ye, Yaoyao Xu, Jiang Wu, Xiaowen Zhang, Wei Liu, Weichen Nikdast, Mahdi A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
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Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC. |
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School of Computer Engineering |
author_facet |
School of Computer Engineering Ye, Yaoyao Xu, Jiang Wu, Xiaowen Zhang, Wei Liu, Weichen Nikdast, Mahdi |
format |
Article |
author |
Ye, Yaoyao Xu, Jiang Wu, Xiaowen Zhang, Wei Liu, Weichen Nikdast, Mahdi |
author_sort |
Ye, Yaoyao |
title |
A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
title_short |
A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
title_full |
A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
title_fullStr |
A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
title_full_unstemmed |
A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
title_sort |
torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/97992 http://hdl.handle.net/10220/12296 |
_version_ |
1681059328501481472 |