A general decoding framework for high-rate LDPC codes
This paper presents a hardware solution to the design of general low-density parity-check (LDPC) decoders,...
Saved in:
Main Authors: | Hosseini, S. M. Ehsan, Goh, Wang Ling, Chan, Kheong Sann |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2010
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/99786 http://hdl.handle.net/10220/6376 http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403795 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
by: Hosseini, S. M. Ehsan, et al.
Published: (2010) -
FPGA implementation of low density parity-check (LDPC) coded recording channels
by: Seyed Mohammad Ehsan Hosseini
Published: (2010) -
LDPC error correction for QKD
by: Tan, Xin Long.
Published: (2013) -
Shortening and turbo decoding of product codes
by: Lim, Kai Ching
Published: (2011) -
Low-complexity detection and decoding for LDPC-coded data storage channels
by: Shaghaghi, Mahdi
Published: (2010)