Design of LUT based RNS reverse converters

• المؤلفون الرئيسيون: Kong, Wei Lam, Vun, Chan Hua
• مؤلفون آخرون: School of Computer Engineering
• التنسيق: Conference or Workshop Item
• اللغة: English
• منشور في: 2013
• الموضوعات: DRNTU::Engineering::Computer science and engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/99797; http://hdl.handle.net/10220/17352
• المؤسسة: Nanyang Technological University

This paper presents the strategies to implement Residue Number System reverse converter based on the Look-Up Table (LUT) approach that is applicable for general moduli set. The approach makes use of partitioning to divide the LUT entries into multiple small LUTs in parallel, where their outputs can be further selected to obtain the equivalent binary number. Pipelining architecture is also incorporated to improve the operation speed. These techniques are hence suitable for general moduli set with large moduli value. Implementation results based on FPGA further demonstrate the feasibility and effectiveness of the proposed approach.