Robust identification and controller design for delay processes

Ph.D

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Bibliographic Details
Main Author:	LIU MIN
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Theses and Dissertations
Language:	English
Published:	2010
Subjects:	Identification, controller design, delay processes
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/13371
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-13371
record_format	dspace
spelling	sg-nus-scholar.10635-133712015-02-10T06:30:16Z Robust identification and controller design for delay processes LIU MIN ELECTRICAL & COMPUTER ENGINEERING WANG QING-GUO HANG CHANG CHIEH Identification, controller design, delay processes Ph.D DOCTOR OF PHILOSOPHY 2010-04-08T10:32:26Z 2010-04-08T10:32:26Z 2007-11-21 Thesis LIU MIN (2007-11-21). Robust identification and controller design for delay processes. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/13371 NOT_IN_WOS en
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
language	English
topic	Identification, controller design, delay processes
spellingShingle	Identification, controller design, delay processes LIU MIN Robust identification and controller design for delay processes
description	Ph.D
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING LIU MIN
format	Theses and Dissertations
author	LIU MIN
author_sort	LIU MIN
title	Robust identification and controller design for delay processes
title_short	Robust identification and controller design for delay processes
title_full	Robust identification and controller design for delay processes
title_fullStr	Robust identification and controller design for delay processes
title_full_unstemmed	Robust identification and controller design for delay processes
title_sort	robust identification and controller design for delay processes
publishDate	2010
url	http://scholarbank.nus.edu.sg/handle/10635/13371
_version_	1681078846452924416

Robust identification and controller design for delay processes

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