The development of building block circuits for high-speed decimation filters
Master's
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2010
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sg-nus-scholar.10635-153332015-02-07T09:46:03Z The development of building block circuits for high-speed decimation filters CHANDRASEKARAN RAJASEKARAN ELECTRICAL & COMPUTER ENGINEERING LIAN YONG CMOS, Differential logic, Decimation filter, Full adder, Flip-Flop, RF digitization Master's MASTER OF ENGINEERING 2010-04-08T10:52:26Z 2010-04-08T10:52:26Z 2006-07-17 Thesis CHANDRASEKARAN RAJASEKARAN (2006-07-17). The development of building block circuits for high-speed decimation filters. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/15333 NOT_IN_WOS en |
institution |
National University of Singapore |
building |
NUS Library |
country |
Singapore |
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ScholarBank@NUS |
language |
English |
topic |
CMOS, Differential logic, Decimation filter, Full adder, Flip-Flop, RF digitization |
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CMOS, Differential logic, Decimation filter, Full adder, Flip-Flop, RF digitization CHANDRASEKARAN RAJASEKARAN The development of building block circuits for high-speed decimation filters |
description |
Master's |
author2 |
ELECTRICAL & COMPUTER ENGINEERING |
author_facet |
ELECTRICAL & COMPUTER ENGINEERING CHANDRASEKARAN RAJASEKARAN |
format |
Theses and Dissertations |
author |
CHANDRASEKARAN RAJASEKARAN |
author_sort |
CHANDRASEKARAN RAJASEKARAN |
title |
The development of building block circuits for high-speed decimation filters |
title_short |
The development of building block circuits for high-speed decimation filters |
title_full |
The development of building block circuits for high-speed decimation filters |
title_fullStr |
The development of building block circuits for high-speed decimation filters |
title_full_unstemmed |
The development of building block circuits for high-speed decimation filters |
title_sort |
development of building block circuits for high-speed decimation filters |
publishDate |
2010 |
url |
http://scholarbank.nus.edu.sg/handle/10635/15333 |
_version_ |
1681079177214689280 |