A 9B 12.5Ms/s PIPELINED CMOS ANALOG TO DIGITAL CONVERTER DESIGN
Master's
Saved in:
Main Author: | LI FENG |
---|---|
Other Authors: | ELECTRICAL ENGINEERING |
Format: | Theses and Dissertations |
Published: |
2020
|
Online Access: | https://scholarbank.nus.edu.sg/handle/10635/172353 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Top-down design verification of subranging pipelined analog-to-digital converter
by: Wang, Jin Ling
Published: (2010) -
Design of CMOS based incremental sigma-delta analog-to-digital converter
by: Gorospe, Rey Andrew P., et al.
Published: (2010) -
Design of an 8-bit CMOS dynamic voltage reference analog-to-digital converter
by: Zhang, Lian
Published: (2016) -
Design of an ultra low-power CMOS analog-to-digital converter for biomedical applications
by: Yuan, Chao
Published: (2014) -
Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology
by: Teh, Jian Sen
Published: (2019)