Instruction cache optimizations for embedded systems

Ph.D

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Bibliographic Details
Main Author: LIANG YUN
Other Authors: COMPUTER SCIENCE
Format: Theses and Dissertations
Language:English
Published: 2010
Subjects:
Online Access:http://scholarbank.nus.edu.sg/handle/10635/18434
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Institution: National University of Singapore
Language: English
id sg-nus-scholar.10635-18434
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spelling sg-nus-scholar.10635-184342024-10-24T18:20:47Z Instruction cache optimizations for embedded systems LIANG YUN COMPUTER SCIENCE TULIKA MITRA embedded systems, instruction cache, cache modeling, design space exploration, cache locking, procedure placement Ph.D DOCTOR OF PHILOSOPHY 2010-10-31T18:01:00Z 2010-10-31T18:01:00Z 2010-07-01 Thesis LIANG YUN (2010-07-01). Instruction cache optimizations for embedded systems. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/18434 NOT_IN_WOS en
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
language English
topic embedded systems, instruction cache, cache modeling, design space exploration, cache locking, procedure placement
spellingShingle embedded systems, instruction cache, cache modeling, design space exploration, cache locking, procedure placement
LIANG YUN
Instruction cache optimizations for embedded systems
description Ph.D
author2 COMPUTER SCIENCE
author_facet COMPUTER SCIENCE
LIANG YUN
format Theses and Dissertations
author LIANG YUN
author_sort LIANG YUN
title Instruction cache optimizations for embedded systems
title_short Instruction cache optimizations for embedded systems
title_full Instruction cache optimizations for embedded systems
title_fullStr Instruction cache optimizations for embedded systems
title_full_unstemmed Instruction cache optimizations for embedded systems
title_sort instruction cache optimizations for embedded systems
publishDate 2010
url http://scholarbank.nus.edu.sg/handle/10635/18434
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