Design and implementation of a high speed and low power flash ADC with fully dynamic comparators
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sg-nus-scholar.10635-237922017-10-21T08:15:47Z Design and implementation of a high speed and low power flash ADC with fully dynamic comparators LI TI ELECTRICAL & COMPUTER ENGINEERING LIAN YONG YAO LIBIN low power, flash ADC, fully dynamic comparators, background calibration, high speed, offset voltage Master's MASTER OF ENGINEERING 2011-07-01T18:01:12Z 2011-07-01T18:01:12Z 2010-01-20 Thesis LI TI (2010-01-20). Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/23792 NOT_IN_WOS en |
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low power, flash ADC, fully dynamic comparators, background calibration, high speed, offset voltage |
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low power, flash ADC, fully dynamic comparators, background calibration, high speed, offset voltage LI TI Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
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Master's |
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ELECTRICAL & COMPUTER ENGINEERING |
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ELECTRICAL & COMPUTER ENGINEERING LI TI |
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Theses and Dissertations |
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LI TI |
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LI TI |
title |
Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
title_short |
Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
title_full |
Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
title_fullStr |
Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
title_full_unstemmed |
Design and implementation of a high speed and low power flash ADC with fully dynamic comparators |
title_sort |
design and implementation of a high speed and low power flash adc with fully dynamic comparators |
publishDate |
2011 |
url |
http://scholarbank.nus.edu.sg/handle/10635/23792 |
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1681080096665894912 |