Method and apparatus for a digital clock multiplication circuit
US6392498
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| Format: | Patent |
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2012
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| Online Access: | http://scholarbank.nus.edu.sg/handle/10635/32610 |
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| Institution: | National University of Singapore |
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sg-nus-scholar.10635-326102015-07-29T07:03:44Z Method and apparatus for a digital clock multiplication circuit LYE, KIN MUN JOE, JURIANTO ELECTRICAL & COMPUTER ENGINEERING CENTRE FOR WIRELESS COMMUNICATIONS THE NATIONAL UNIVERSITY OF SINGAPORE US6392498 Granted Patent 2012-05-02T02:27:45Z 2012-05-02T02:27:45Z 2002-05-21 Patent LYE, KIN MUN,JOE, JURIANTO (2002-05-21). Method and apparatus for a digital clock multiplication circuit. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/32610 NOT_IN_WOS PatSnap |
| institution |
National University of Singapore |
| building |
NUS Library |
| country |
Singapore |
| collection |
ScholarBank@NUS |
| description |
US6392498 |
| author2 |
ELECTRICAL & COMPUTER ENGINEERING |
| author_facet |
ELECTRICAL & COMPUTER ENGINEERING LYE, KIN MUN JOE, JURIANTO |
| format |
Patent |
| author |
LYE, KIN MUN JOE, JURIANTO |
| spellingShingle |
LYE, KIN MUN JOE, JURIANTO Method and apparatus for a digital clock multiplication circuit |
| author_sort |
LYE, KIN MUN |
| title |
Method and apparatus for a digital clock multiplication circuit |
| title_short |
Method and apparatus for a digital clock multiplication circuit |
| title_full |
Method and apparatus for a digital clock multiplication circuit |
| title_fullStr |
Method and apparatus for a digital clock multiplication circuit |
| title_full_unstemmed |
Method and apparatus for a digital clock multiplication circuit |
| title_sort |
method and apparatus for a digital clock multiplication circuit |
| publishDate |
2012 |
| url |
http://scholarbank.nus.edu.sg/handle/10635/32610 |
| _version_ |
1681081254858981376 |