Method and apparatus for a digital clock multiplication circuit
US20030006850A1
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| Format: | Patent |
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2012
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| Online Access: | http://scholarbank.nus.edu.sg/handle/10635/34916 |
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| Institution: | National University of Singapore |
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sg-nus-scholar.10635-349162024-11-10T21:44:03Z Method and apparatus for a digital clock multiplication circuit LYE, KIN MUN JOE, JURIANTO ELECTRICAL & COMPUTER ENGINEERING THE NATIONAL UNIVERSITY OF SINGAPORE US20030006850A1 Published Application 2012-10-08T08:22:39Z 2012-10-08T08:22:39Z 2003-01-09 Patent LYE, KIN MUN,JOE, JURIANTO (2003-01-09). Method and apparatus for a digital clock multiplication circuit. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/34916 NOT_IN_WOS PatSnap |
| institution |
National University of Singapore |
| building |
NUS Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NUS Library |
| collection |
ScholarBank@NUS |
| description |
US20030006850A1 |
| author2 |
ELECTRICAL & COMPUTER ENGINEERING |
| author_facet |
ELECTRICAL & COMPUTER ENGINEERING LYE, KIN MUN JOE, JURIANTO |
| format |
Patent |
| author |
LYE, KIN MUN JOE, JURIANTO |
| spellingShingle |
LYE, KIN MUN JOE, JURIANTO Method and apparatus for a digital clock multiplication circuit |
| author_sort |
LYE, KIN MUN |
| title |
Method and apparatus for a digital clock multiplication circuit |
| title_short |
Method and apparatus for a digital clock multiplication circuit |
| title_full |
Method and apparatus for a digital clock multiplication circuit |
| title_fullStr |
Method and apparatus for a digital clock multiplication circuit |
| title_full_unstemmed |
Method and apparatus for a digital clock multiplication circuit |
| title_sort |
method and apparatus for a digital clock multiplication circuit |
| publishDate |
2012 |
| url |
http://scholarbank.nus.edu.sg/handle/10635/34916 |
| _version_ |
1821200840310915072 |